1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device in which a low voltage operation, low power consumption and a high driving capacity are required, particularly to a power management semiconductor device such as a voltage detector (hereinafter referred to as VD), a voltage regulator (hereinafter referred to as VR) or a switching regulator (hereinafter referred to as SWR) or an analog semiconductor device such as an operational amplifier or a comparator.
2. Description of the Related Art
FIG. 89 is a schematic cross sectional view of a conventional semiconductor device. The semiconductor device is composed of a complementary MOS structure (hereinafter referred to as NMOS) in which a gate electrode formed on a P-type semiconductor substrate is comprised of N+ type polycrystalline silicon and a P-channel MOS transistor 212 (hereinafter referred to as PMOS) in which a gate electrode formed in an N-well region is also comprised of N+type polycrystalline silicon, and a resistor 215 used in a voltage dividing circuit for dividing a voltage which is formed on a field insulating film or a CR circuit for setting a time constant. The resistor is formed of a polycrystalline silicon that is the same layer as a gate electrode of CMOS with N-type conductivity and has the same conductivity type in terms of simplicity and ease of a method of manufacturing thereof.
In the semiconductor device with the above conventional structure, since an enhancement type NMOS (hereinafter referred to as E-type NMOS) with a voltage of approximately 0.7 V that is a standard threshold voltage has a gate electrode comprised of N+polycrystalline silicon, a channel is a surface channel formed on a surface of a semiconductor substrate in accordance with the relationship of working functions of the gate electrode and the semiconductor substrate. On the other hand, in an enhancement type PMOS (hereinafter referred to as E-type PMOS) with a voltage of approximately xe2x88x920.7 V that is a standard threshold voltage, a channel is a buried channel somewhat formed in an inner side from the surface of the semiconductor substrate in accordance with the relationship of working functions of the gate electrode comprised of N+polycrystalline silicon and the N-well.
In the buried channel E-type PMOS, in the case where the threshold voltage is set to, for example, xe2x88x920.5 V or more for low voltage operation, a subthreshold characteristic, which is one index of low voltage operation of a MOS transistor, extremely deteriorates, and thus, a leak current at the off time the PMOS increases. As a result, consumption current at the time of waiting of the semiconductor device remarkably increases. Thus, there is a problem in that it is difficult to apply the semiconductor device to portable apparatuses typified by a portable telephone and a portable terminal which are greatly demanded in recent years and the market for which is predicted to further develop in the future.
As technical means for attaining the above-described problems, both the low voltage operation and the low consumption current, the homopolar gate technique is generally known, in which the conductivity type of an NMOS gate electrode is set as N-type and the conductivity type of a PMOS gate electrode is set as P-type. In this case, both the E-type NMOS and the E-type PMOS are surface channel MOS transistors, and therefore, the lowering of the threshold voltage does not lead to the extreme deterioration of a sub-threshold coefficient. Thus, the low voltage operation and the low power consumption are possible.
However, the homopolar gate CMOS has a problem in that increases of the number of steps, the manufacturing cost, and the manufacturing period are caused in comparison with the CMOS in which the gate electrode is only N+polycrystalline silicon monopole since the gate polarities are separately formed for the NMOS and PMOS in the manufacturing process.
Further, a reference voltage circuit is given as an important element circuit constituting a power management semiconductor device such as VD, VR and SWR. The reference voltage circuit always outputs a constant voltage from an output terminal with respect to the electric potential of a low voltage supply terminal irrespective of the electric potential of a high voltage supply terminal. The reference voltage circuit is constituted of an E-type NMOS and a depletion type NMOS (hereinafter referred to as D-type NMOS) with series connection in many cases. In the case where the polarity of the gate electrode is N-type, the E-type NMOS is a surface channel while the D-NMOS is a buried channel in accordance with the relationship of working functions of the gate and the well or substrate. As an important characteristic of the reference voltage circuit, there is given a small change of an output voltage to a change of temperature. However, the threshold voltage of MOS and the degree of change to the temperature change of mutual conductance are largely different between the surface channel and the buried channel. As a result, the reference voltage circuit has a problem in that it is difficult to reduce the change of an output voltage to the temperature change.
The present invention has been made in view of the above, and an object of the present invention is therefore to provide a structure that enables the materialization of a power management semiconductor device or an analog semiconductor device in which the low cost, short manufacturing period, low voltage operation and low power consumption are attained.
In order to solve the above-mentioned problems, the present invention employs the following measures.
According to the present invention, there is provided a complementary MOS semiconductor device having an N-channel MOS transistor, a P-channel MOS transistor and a resistor, characterized in that a conductivity type of a gate electrode of the N-channel MOS transistor is P-type, and a conductivity type of a gate electrode of the P-channel MOS transistor is P-type.
Further, according to the present invention, here is provided a complementary MOS semiconductor device, characterized in that the P-type gate electrode of the N-channel MOS transistor and the P-type gate electrode of the P-channel MOS transistor each comprise a single layer of first polycrystalline silicon having a film thickness in a range of 2000 xc3x85 to 6000 xc3x85 and including boron or BF2 with an impurity concentration of 1xc3x971019 atoms/cm3 or more.
Further, according to the present invention, there is provided a complementary MOS semiconductor device, characterized in that the P-type gate electrode of the N-channel MOS transistor and the P-type gate electrode of the P-channel MOS transistor each have a polycide structure comprising a lamination of first polycrystalline silicon having a film thickness in a range of 1000 xc3x85 to 4000 xc3x85 and including boron or BF2 with an impurity concentration of 1xc3x971019 atoms/cm3 or more and first high melting point metal silicide selected from the group consisting of molybdenum silicide, tungsten silicide, titanium silicide, and platinum silicide, with a film thickness in a range of 500 xc3x85 to 2500 xc3x85.
Further, according to the present invention, there is provided a complementary MOS semiconductor device, characterized in that the resistor is polycrystalline silicon formed in the same layer and has the same film thickness range as the first polycrystalline silicon constituting the gate electrode.
Further, according to the present invention, there is provided a complementary MOS semiconductor device, characterized in that the resistor is second polycrystalline silicon having a film thickness in a range of 500 xc3x85 to 2000 xc3x85.
Further, according to the present invention, there is provided a complementary MOS semiconductor device, characterized in that the resistor is a thin film metal transistor formed from one selected from the group consisting of Nixe2x80x94Cr alloy, Crxe2x80x94SiO alloy, molybdenum silicide, and xcex2-ferrite silicide and has a film thickness in a range of 100 xc3x85 to 300 xc3x85.
Further, according to the present invention, there is provided a complementary MOS semiconductor device, characterized in that the resistor comprising the first or the second polycrystalline silicon contains phosphorous or arsenic with an impurity concentration of 1xc3x971014 to 9xc3x971018 atoms/cm3 and includes a first N-type transistor of a relatively low concentration having a sheet resistance in an order of several kxcexa9/square to several tens of kxcexa9/square.
Further, according to the present invention, there is provided a complementary MOS semiconductor device, characterized in that the resistor comprising the first or the second polycrystalline silicon contains phosphorous or arsenic with an impurity concentration of 1xc3x971019 atoms/cm3 or more and includes a second N-type transistor of a relatively high concentration having a sheet resistance in an order of about 100 xcexa9/square to several hundreds of xcexa9/square and a temperature coefficient in an order of several hundreds of ppm/xc2x0 C. to about 1000 ppm/xc2x0 C.
Further, according to the present invention, there is provided a complementary MOS semiconductor device, characterized in that the resistor comprising the first or the second polycrystalline silicon contains boron or BF2 with an impurity concentration of 1xc3x971014 to 9xc3x971019 atoms/cm3 and includes a first P-type transistor of a relatively low concentration having a sheet resistance in an order of several kxcexa9/square to several tens of kxcexa9/square.
Further, according to the present invention, there is provided a complementary MOS semiconductor device, characterized in that the resistor comprising the first or the second polycrystalline silicon contains boron or BF2 with an impurity concentration of 1xc3x971019 atoms/cm3 or more and includes a second P-type transistor of a relatively high concentration having a sheet resistance in an order of several hundreds of xcexa9/square to about 1 kxcexa9/square and a temperature coefficient in an order of several hundreds of ppm/xc2x0 C. to about 1000 ppm/xc2x0 C.
Further, according to the present invention, there is provided a complementary MOS semiconductor device, characterized in that the N-channel MOS transistor and the P-channel MOS transistor include a MOS transistor having a first structure of a single drain structure comprising a diffusion layer with a high impurity concentration in which a source and a drain overlap the P-type gate electrode in a planar manner.
Further, according to the present invention, there is provided a complementary MOS semiconductor device, characterized in that the N-channel MOS transistor and the P-channel MOS transistor include a MOS transistor having a second structure comprising a diffusion layer with a low impurity concentration in which only the drain side thereof overlaps the P-type gate electrode in a planar manner or both the source and drain sides thereof overlap the P-type gate electrode in the planar manner and a diffusion layer with a high impurity concentration in which only the drain side thereof does not overlap the P-type gate electrode in the planar manner or both the source and drain sides thereof do not overlap the P-type gate electrode in the planar manner.
Further, according to the present invention, there is provided a complementary MOS semiconductor device, characterized in that the N-channel MOS transistor and the P-channel MOS transistor include a MOS transistor having a third structure comprising a diffusion layer with a low impurity concentration in which only the drain side thereof overlaps the P-type gate electrode in a planar manner or both the source and drain side thereof overlap the P-type gate electrode in the planar manner and a diffusion layer with a high impurity concentration in which only the drain side thereof does not overlap the P-type gate electrode in the planar manner or both the source and drain sides thereof do not overlap the P-type gate electrode in the planar manner, and an insulating film between the diffusion layer wit a high impurity concentration and the P-type gate electrode has a film thickness thicker than that of a gate insulating film.
Further, according to the present invention, there is provided a complementary MOS semiconductor device, characterized in that the N-channel MOS transistor and the P-channel MOS transistor include a MOS transistor having a fourth structure comprising a diffusion layer with a high impurity concentration in which both the source and the drain overlap the P-type gate electrode in a planar manner and a diffusion layer with a low impurity concentration which only the drain side thereof or both the source and drain sides thereof diffuse further on the channel side to overlap the P-type gate electrode in the planar manner.
Further, according to the present invention, there is provided a complementary MOS semiconductor device, characterized in that, in the N-channel MOS transistor, a channel in which a threshold voltage is in enhancement is a buried channel.
Further, according to the present invention, there is provided a complementary MOS semiconductor device, characterized in that, in the P-channel MOS transistor, a channel in which a threshold voltage is in enhancement is a surface channel.
Further, according to the present invention, there is provided a complementary MOS semiconductor device, characterized in that the low impurity concentration diffusion layers in the second structure MOS transistor, the third structure MOS transistor and the fourth structure MOS transistor use arsenic or phosphorous as an impurity with an impurity concentration of 1xc3x971016 to 1xc3x971018 atoms/cm3 in the N-channel MOS transistor and use boron or BF2 as the impurity with an impurity concentration of 1xc3x971016 to 1xc3x971018 atoms/cm3 the P-channel MOS transistor, and the high impurity concentration diffusion layers in the first structure MOS transistor, the second structure MOS transistor, the third structure MOS transistor and the fourth structure MOS transistor use arsenic or phosphorous as the impurity with an impurity concentration of 1xc3x971016 to 1xc3x971018 atoms/cm3 or more in the N-channel MOS transistor and uses boron or BF2 as the impurity with an impurity concentration of 1xc3x971016 to 1xc3x971018 atoms/cm3 or more in the P-channel MOS transistor.
Further, according to the present invention, there is provided a method of manufacturing a complementary MOS semiconductor device, comprising the steps of:
forming wells for defining respective regions of an N-channel MOS transistor and a P-channel MOS transistor in a semiconductor substrate;
forming an element isolating region on the semiconductor substrate;
forming a gate insulating film on the semiconductor substrate;
doping an impurity for controlling a threshold value into the semiconductor substrate;
forming a first polycrystalline silicon film on the semiconductor substrate;
selectively doping a low concentration N-type impurity into the first polycrystalline silicon film to form a first N-type region in the first polycrystalline silicon film;
selectively doping a high concentration P-type impurity into the first polycrystalline silicon film to form a first P-type region in the first polycrystalline silicon film;
doping a low concentration P-type impurity into an entire region of the first polycrystalline silicon film to form a second P-type region in the first polycrystalline silicon film;
forming a first insulating film on the first polycrystalline silicon film;
patterning the first insulating film and the first polycrystalline silicon film to form a gate electrode and a wiring formed of the first P-type polycrystalline silicon region and a resistor formed of the first N-type polycrystalline silicon region and the second P-type polycrystalline silicon region;
selectively removing the first insulating film on the resistor;
doping a high concentration N-type impurity into regions that become a source and a drain of the N-channel MOS transistor and a part or an entire region of the resistor formed of the first N-type polycrystalline silicon region; and
doping a high concentration P-type impurity into regions that become a source and a drain of the P-channel MOS transistor and a part or an entire region of the resistor formed of the second P-type polycrystalline silicon region.
Further, according to the present invention, there is provided a method of manufacturing a complementary MOS semiconductor device, comprising the steps of:
forming wells for defining respective regions of an N-channel MOS transistor and a P-channel MOS transistor in a semiconductor substrate;
forming an element isolating region on the semiconductor substrate;
forming a gate insulating film on the semiconductor substrate;
doping an impurity for controlling a threshold value into the semiconductor substrate;
forming a first polycrystalline silicon film on the semiconductor substrate;
doping a high concentration P-type impurity into an entire region of the first polycrystalline silicon film to form a first P-type region of a first polycrystalline silicon film;
forming a high melting point metal silicide film on the first polycrystalline silicon film;
forming a first insulating film on the high melting point metal silicide film;
patterning the first insulating film, the high melting point metal silicide film and the first polycrystalline silicon film of the first P-type region to form a gate electrode and a wiring;
forming a fourth insulating film on the semiconductor substrate;
forming a second polycrystalline silicon film on the fourth insulating film;
selectively doping a low concentration N-type impurity into the second polycrystalline silicon film to form a first N-type region in the second polycrystalline silicon film;
doping a low concentration P-type impurity into an entire region of the second polycrystalline silicon film to form a second P-type region in the second polycrystalline silicon film;
patterning the second polycrystalline silicon film to form a resistor;
doping a high concentration N-type impurity into regions that become a source and a drain of the N-channel MOS transistor and a part or an entire region of the resistor formed of the first N-type polycrystalline silicon region; and
doping a high concentration P-type impurity into regions that become a source and a drain of the P-channel MOS transistor and a part or an entire region of the resistor formed of the second P-type polycrystalline silicon region.
Further, according to the present invention, there is provided a method of manufacturing a complementary MOS semiconductor device, comprising the steps of:
forming walls for defining respective regions of an N-channel MOS transistor and a P-channel MOS transistor in a semiconductor substrate;
forming an element isolating region on the semiconductor substrate;
forming a gate insulating film on the semiconductor substrate;
doping an impurity for controlling a threshold value into the semiconductor substrate;
forming a first polycrystalline silicon film on the semiconductor substrate;
doping a high concentration P-type impurity into an entire region of the first polycrystalline silicon film to form a first P-type region of a first polycrystalline silicon film;
forming a high melting point metal film on the first polycrystalline silicon film;
performing heat treatment for the high melting point metal film, which contacts to the first polycrystalline silicon film, to obtain a high melting point metal silicide film;
forming a first insulating film on the high melting point metal silicide film;
patterning the first insulating film, the high melting point metal silicide film and the first polycrystalline silicon film of the first P-type region to form a gate electrode and a wiring;
forming a fourth insulating film on the semiconductor substrate;
forming a second polycrystalline silicon film on the fourth insulating film;
selectively doping a low concentration N-type impurity into the second polycrystalline silicon film to form a first N-type region in the second polycrystalline silicon film;
doping a low concentration P-type impurity into an entire region of the second polycrystalline silicon film to form a second P-type region in the second polycrystalline silicon film;
patterning the second polycrystalline silicon film to form a resistor;
doping a high concentration N-type impurity into regions that become a source and a drain of the N-channel MOS transistor and a part or an entire region of the resistor formed of the first N-type polycrystalline silicon-region; and
doping a high concentration P-type impurity into regions that become a source and a drain of the P-channel MOS transistor and a part or an entire region of the resistor formed of the second P-type polycrystalline silicon region.
Further, according to the present invention, there is provided a method of manufacturing a complementary MOS semiconductor device, comprising the steps or:
forming wells for defining respective regions of an N-channel MOS transistor and a P-channel MOS transistor in a semiconductor substrate;
forming an element isolating region on the semiconductor substrate;
forming a gate insulating film on the semiconductor substrate;
doping an impurity for controlling a threshold value into the semiconductor substrate;
forming a first polycrystalline silicon film on the semiconductor substrate;
selectively doping a low concentration N-type impurity into the first polycrystalline silicon film to form a first N-type region in the first polycrystalline silicon film;
selectively doping a high concentration P-type impurity into the first polycrystalline silicon film to form a first P-type region in the first polycrystalline silicon film;
doping a low concentration P-type impurity into an entire region of he first polycrystalline silicon film to form a second P-type region in the first polycrystalline silicon film;
forming a first insulating film on the first polycrystalline silicon film;
patterning the first insulating film and the first polycrystalline silicon film to form a gate electrode and a wiring formed of the first P-type polycrystalline silicon region and a resistor formed of the first N-type polycrystalline silicon region and the second P-type polycrystalline silicon region;
selectively doping a low concentration N-type impurity into regions that become a source and a drain of the N-channel MOS transistor in the semiconductor substrate; and
doping a low concentration P-type impurity into regions that become a source and a drain of the P-channel MOS transistor in the semiconductor substrate;
depositing a third insulating film on the semiconductor substrate;
etching the third insulating film by anisotropic dry etching to form a side spacer on a side wall of the first polycrystalline silicon film;
selectively removing the first insulating film on the resistor;
doping a high concentration N-type impurity into regions that become a source and a drain of the N-channel MOS transistor and a part or an entire region of the resistor formed of the first N-type region of the first polycrystalline silicon; and
doping a high concentration P-type impurity into regions that become a source and a drain of the P-channel MOS transistor and a part or an entire region of the resistor formed of the second P-type region of the first polycrystalline silicon.
Further, according to the present invention, there is provided a method of manufacturing a complementary MOS semiconductor device, comprising the steps of:
forming wells for defining respective regions of an N-channel MOS transistor and a P-channel MOS transistor in a semiconductor substrate;
forming an element isolating region on the semiconductor substrate;
forming a gate insulating film on the semiconductor substrate;
doping an impurity for controlling a threshold value into the semiconductor substrate;
forming a first polycrystalline silicon film on the semiconductor substrate;
selectively doping a high concentration P-type impurity into the first polycrystalline silicon film to form a first P-type region in the first polycrystalline silicon film;
forming a first insulating film on the first polycrystalline silicon film;
patterning the first insulating film and the first polycrystalline silicon film to form a gate electrode and a wiring formed of the first P-type polycrystalline silicon region and a resistor region formed of the region other than the first P-type polycrystalline silicon film region;
selectively removing the first insulating film on the resistor region;
selectively doping a low concentration N-type impurity into regions that become a source and a drain of the N-channel MOS transistor and into the polycrystalline silicon film other than the first P-type polycrystalline silicon film region to form a low concentration N-type source and drain and a first N-type region in the first polycrystalline silicon film;
selectively doping a low concentration P-type impurity into regions that become the source and the drain of the P-channel MOS transistor and into the first polycrystalline silicon film other than the first P-type polycrystalline silicon film region and the first N-type polycrystalline silicon film region to form a low concentration P-type source and drain and a second P-type region in the first polycrystalline silicon film;
depositing a third insulating film on the semiconductor substrate;
etching the third insulating film by anisotropic dry etching to form a side spacer on a side wall of the first polycrystalline silicon film;
doping a high concentration N-type impurity into regions that become the source and the drain of the N-channel MOS transistor and a part or an entire region of the resistor formed of the first N-type region of the first polycrystalline silicon; and
doping a high concentration P-type impurity into regions that become the source and the drain of the P-channel MOS transistor and a part or an entire region of the resistor formed of the second P-type region of the first polycrystalline silicon.
Further, according to the present invention, there is provided a method of manufacturing a complementary MOS semiconductor device, comprising the steps of:
forming wells for defining respective regions of an N-channel MOS transistor and a P-channel MOS transistor in a semiconductor substrate;
forming an element isolating region on the semiconductor substrate;
forming a gate insulating film on the semiconductor substrate;
doping an impurity for controlling a threshold value into the semiconductor substrate;
forming a first polycrystalline silicon film on the semiconductor substrate;
doping a high concentration P-type impurity into the first polycrystalline silicon film to form a first P-type polycrystalline silicon region;
forming a first insulating film on the first polycrystalline silicon film;
patterning the first insulating film and the first polycrystalline silicon film to form a gate electrode and a wiring formed of the first polycrystalline silicon region;
selectively doping a low concentration N-type impurity into regions that become a source and a drain of the N-channel MOS transistor in the semiconductor substrate;
selectively doping a low concentration P-type impurity into regions that become the source and the drain of the P-channel MOS transistor in the semiconductor device;
depositing a third insulating film on the semiconductor substrate;
etching the third insulating film by anisotropic dry etching to form a side spacer on a side wall of the first polycrystalline silicon film;
forming a second polycrystalline silicon film on the semiconductor substrate;
selectively doping a low concentration N-type impurity into the second polycrystalline silicon film to form a first N-type impurity region;
doping a low concentration P-type impurity into an entire region of the second polycrystalline silicon film to form a second P-type polycrystalline silicon region;
patterning the second polycrystalline silicon film to form a resistor;
selectively doping a high concentration N-type impurity into regions that become the source and the drain of the N-channel MOS transistor and a part or an entire region of the resistor formed of the first N-type region of the second polycrystalline silicon; and
selectively doping a high concentration P-type impurity into regions that become the source and the drain of the P-channel MOS transistor and a part or an entire region of the resistor formed of the second P-type region of the second polycrystalline silicon.
Further, according to the present invention, there is provided a method of manufacturing a complementary MOS semiconductor device, comprising the steps of:
forming wells for defining respective regions of an N-channel MOS transistor and a P-channel MOS transistor in a semiconductor substrate;
forming an element isolating region on the semiconductor substrate;
forming a gate insulating film on the semiconductor substrate;
doping an impurity for controlling a threshold value into the semiconductor substrate;
forming a first polycrystalline silicon film on the semiconductor substrate;
selectively doping a low concentration N-type impurity into the first polycrystalline silicon film to form a first N-type polycrystalline silicon region;
selectively doping a high concentration P-type impurity into the first polycrystalline silicon film to form a first P-type polycrystalline silicon region;
doping a low concentration P-type impurity into an entire region of the first polycrystalline silicon film to form a second P-type polycrystalline silicon region;
forming a second insulating film on the first polycrystalline silicon film;
selectively removing the second insulating film on the first P-type region of the first polycrystalline silicon film;
forming a high melting point metal silicide film on the semiconductor substrate;
selectively removing the high melting point metal silicide film on the patterned second insulating film and in the vicinity thereof;
removing the patterned second insulating film;
forming a first insulating film on the high melting point metal silicide film and the first polycrystalline silicon film;
patterning the first insulating film, the first polycrystalline silicon film and the high melting point metal silicide film to form a gate electrode and a wiring formed of a lamination layer of the first P-type region of the first polycrystalline silicon film and the high melting point metal silicide film and a resistor formed of the first N-type region and the second P-type region of the first polycrystalline silicon film;
selectively doping a low concentration N-type impurity into regions that become the source and the drain of the N-channel MOS transistor in the semiconductor substrate;
selectively doping a low concentration P-type impurity into regions that become the source and the drain of the P-channel MOS transistor in the semiconductor substrate;
depositing a third insulating film on the semiconductor substrate;
etching the third insulating film by anisotropic dry etching to form side spacers to side walls of the first polycrystalline silicon film and the high melting point metal silicide film;
selectively removing the first insulating film on the resistor;
doping a high concentration N-type impurity into regions that become the source and the drain of the N-channel MOS transistor and a part or an entire region of the resistor formed of the first N-type polycrystalline silicon region; and
doping a high concentration P-type impurity into regions that become the source and the drain of the P-channel MOS transistor and a part or an entire region of the resistor formed of the second P-type polycrystalline silicon region.
Further, according to the present invention, there is provided a method of manufacturing a complementary MOS semiconductor device, comprising the steps of:
forming wells for defining respective regions of an N-channel MOS transistor and a P-channel MOS transistor in a semiconductor substrate;
forming an element isolating region on the semiconductor substrate;
forming a gate insulating film on the semiconductor substrate;
doping an impurity for controlling a threshold value into the semiconductor substrate;
forming a first polycrystalline silicon film on the semiconductor substrate;
selectively doping a high concentration P-type impurity into the first polycrystalline silicon film to form a first P-type polycrystalline silicon region;
forming a second insulating film on the first polycrystalline silicon film;
selectively removing the second insulating film on the first P-type region of the first polycrystalline silicon film;
forming a high melting point metal silicide film on the semiconductor substrate;
selectively removing the high melting point metal silicide film on the patterned second insulating film and in the vicinity thereof;
removing the patterned second insulating film;
forming a first insulating film on the high melting point metal silicide film and the first polycrystalline silicon film;
patterning the first insulating film, the first polycrystalline silicon film and the high melting point metal silicide film to form a gate electrode and a wiring formed of a lamination layer of the first P-type region of the first polycrystalline silicon film and the high melting point metal silicide film and a resistor region formed of the region other than the first P-type region of the first polycrystalline silicon film;
selectively removing the first insulating film on the resistor region;
selectively doping a low concentration N-type impurity into regions that become the source and the drain of the N-channel MOS transistor and the first polycrystalline silicon film other than the first P-type region to form a low concentration N-type source and drain and a first N-type region in the first polycrystalline silicon film;
selectively doping a low concentration P-type impurity into regions that become the source and the drain of the P-channel MOS transistor and the first polycrystalline silicon film other than the first P-type region and the first N-type region to form a low concentration P-type source and drain and a second P-type region in the first polycrystalline silicon film;
depositing a third insulating film on the semiconductor substrate;
etching the third insulating film by anisotropic dry etching to form side spacers on side walls of the first polycrystalline silicon film and the high melting point metal silicide film;
doping a high concentration N-type impurity into regions that become the source and the drain of the N-channel MOS transistor and a part or an entire region of the resistor formed of the first N-type polycrystalline silicon region; and
doping a high concentration P-type impurity into regions that become the source and the drain or the P-channel MOS transistor and a part or an entire region of the resistor formed of the second P-type polycrystalline silicon region.
Further, according to the present invention, there is provided a method of manufacturing a complementary MOS semiconductor device, comprising the steps of:
forming wells for defining respective regions of an N-channel MOS transistor and a P-channel MOS transistor in a semiconductor substrate;
forming an element isolating region on the semiconductor substrate;
forming a gate insulating film on the semiconductor substrate;
doping an impurity for controlling a threshold value into the semiconductor substrate;
forming a first polycrystalline silicon film on the semiconductor substrate;
selectively doping a low concentration N-type impurity into the first polycrystalline silicon film to form a first N-type polycrystalline silicon region;
selectively doping a high concentration P-type impurity into the first polycrystalline silicon film to form a first P-type polycrystalline silicon region;
doping a low concentration P-type impurity into an entire region of the first polycrystalline silicon film to form a second P-type polycrystalline silicon region;
forming a second insulating film on the first polycrystalline silicon film;
selectively removing the second insulating film on the first P-type region of the first polycrystalline silicon film;
forming a high melting point metal silicide film on the semiconductor substrate;
performing heat treatment for the high melting point metal film, which contacts to the first polycrystalline silicon film, to obtain a high melting point metal silicide film;
selectively removing non-reacted high melting point metal silicide film on the second insulating film;
removing the patterned second insulating film;
forming a first insulating film on the high melting point metal silicide film and the first polycrystalline silicon film;
patterning the first insulating film, the first polycrystalline silicon film and the high melting point metal silicide film to form a gate electrode and a wiring formed of a lamination layer of the first P-type region of the first polycrystalline silicon film and the high melting point metal silicide film and a resistor formed of the first N-type region and the second P-type region of the first polycrystalline silicon film;
selectively doping a low concentration N-type impurity into regions that become the source and the drain of the N-channel MOS transistor in the semiconductor substrate;
selectively doping a low concentration P-type impurity into regions that become the source and the drain of the P-channel MOS transistor in the semiconductor substrate;
depositing a third insulating film on the semiconductor substrate;
etching the third insulating film by anisotropic dry etching to form side spacers on side walls of the first polycrystalline silicon film and the high melting point metal silicide film;
selectively removing the first insulating film on the resistor;
doping a high concentration N-type impurity into regions that become the source and the drain of the N-channel MOS transistor and a part or an entire region of the resistor formed of the first N-type polycrystalline silicon region; and
doping a high concentration P-type impurity into regions that become the source and the drain of the P-channel MOS transistor and a part or an entire region of the resistor formed of the second P-type polycrystalline silicon region.
Further, according to the present invention, there is provided a method of manufacturing a complementary MOS semiconductor device, comprising the steps of:
forming wells for defining respective regions of an N-channel MOS transistor and a P-channel MOS transistor in a semiconductor substrate;
forming an element isolating region on the semiconductor substrate;
forming a gate insulating film on the semiconductor substrate;
doping an impurity for controlling a threshold value into the semiconductor substrate;
forming a first polycrystalline silicon film on the semiconductor substrate;
selectively doping a high concentration P-type impurity into the first polycrystalline silicon film to form a first P-type polycrystalline silicon region;
forming a second insulating film on the first polycrystalline silicon film;
selectively removing the second insulating film on the first P-type region of the first polycrystalline silicon film;
forming a high melting point metal silicide film on the semiconductor substrate;
performing heat treatment for the high melting point metal film, which contacts to the first polycrystalline silicon film, to obtain a high melting point metal silicide film;
selectively removing non-reacted high melting point metal silicide film on the second insulating film;
removing the patterned second insulating film;
forming a first insulating film on the high melting point metal silicide film and the first polycrystalline silicon film;
patterning the first insulating film, the first polycrystalline silicon film and the high melting point metal silicide film to form a gate electrode and a wiring formed of a lamination layer of the first P-type region of the first polycrystalline silicon film and the high melting point metal silicide film and a resistor region formed of the region other than the first P-type region of the first polycrystalline silicon film;
selectively removing the first insulating film on the resistor region;
selectively doping a low concentration N-type impurity into regions that become the source and the drain of the N-channel MOS transistor and the first polycrystalline silicon film other than the first P-type region to form a low concentration N-type source and drain and a first N-type region in the first polycrystalline silicon film;
selectively doping a low concentration P-type impurity into regions that become the source and the drain of the P-channel MOS transistor and the first polycrystalline silicon film other than the first P-type region and the first N-type region to form a low concentration P-type source and drain and a second P-type region in the first polycrystalline silicon film;
depositing a third insulating film on the semiconductor substrate;
etching the third insulating film by anisotropic dry etching to form side spacers on side walls of the first polycrystalline silicon film and the high melting point metal silicide film;
doping a high concentration N-type impurity into regions that become the source and the drain of the N-channel MOS transistor and a part or an entire region of the resistor formed of the first N-type polycrystalline silicon region; and
doping a high concentration P-type impurity into regions that become the source and the drain of the P-channel MOS transistor and a part or an entire region of the resistor formed of the second P-type polycrystalline silicon region.
Further, according to the present invention, there is provided a method of manufacturing a complementary MOS semiconductor device, comprising the steps of:
forming wells for defining respective regions of an N-channel MOS transistor and a P-channel MOS transistor in a semiconductor substrate;
forming an element isolating region on the semiconductor substrate;
forming a gate insulating film on the semiconductor substrate;
doping an impurity for controlling a threshold value into the semiconductor substrate;
forming a first polycrystalline silicon film on the semiconductor substrate;
doping a high concentration P-type impurity into an entire region of the first polycrystalline silicon film to form a first P-type region in the first polycrystalline silicon film;
forming a high melting point metal silicide film on the first polycrystalline silicon film;
forming a first insulating film on the high melting point metal silicide film;
patterning the first insulating film, the high melting point metal silicide film and the first polycrystalline silicon film of the first P-type region to form a gate electrode and a wiring;
selectively doping a low concentration N-type impurity into regions that become the source and the drain of the N-channel MOS transistor in the semiconductor substrate;
selectively doping a low concentration P-type impurity into regions that become the source and the drain of the P-channel MOS transistor in the semiconductor substrate;
depositing a third insulating film on the semiconductor substrate;
etching the third insulating film by anisotropic dry etching to form side spacers on side walls of the first polycrystalline silicon film and the high melting point metal silicide film;
forming a second polycrystalline silicon film on the semiconductor substrate;
selectively doping a low concentration N-type impurity into the second polycrystalline silicon film to form a first N-type polycrystalline silicon region;
doping a low concentration P-type impurity into an entire region of the second polycrystalline silicon film to form a second P-type polycrystalline silicon region;
patterning the second polycrystalline silicon film to form a resistor;
selectively doping a high concentration N-type impurity into region that become the source and the drain of the N-channel MOS transistor and a part or an entire region of the resistor formed of the first N-type region of the second polycrystalline silicon region; and
selectively doping a high concentration P-type impurity into regions that become the source and the drain of the P-channel MOS transistor and a part or an entire region of the resistor formed of the second P-type region of the second polycrystalline silicon.
Further, according to the present invention, there is provided a method of manufacturing a complementary MOS semiconductor device, comprising the steps of:
forming wells for defining respective regions of an N-channel MOS transistor and a P-channel MOS transistor in a semiconductor substrate;
forming an element isolating region on the semiconductor substrate;
forming a gate insulating film on the semiconductor substrate;
doping an impurity for controlling a threshold value into the semiconductor substrate;
forming a first polycrystalline silicon film on the semiconductor substrate;
doping a high concentration P-type impurity into an entire region of the first polycrystalline silicon film to form a first P-type region in the first polycrystalline silicon film;
forming a high melting point metal film on the first polycrystalline silicon film;
performing heat treatment for the high melting point metal film, which contacts to the first polycrystalline silicon film, to obtain a high melting point metal silicide film;
forming a first insulating film, the high melting point metal silicide film;
patterning the first insulating film, the high melting point metal silicide film and the first polycrystalline silicon to form a gate electrode and a wiring;
selectively doping a low concentration N-type impurity into regions that become the source and the drain of the N-channel MOS transistor in the semiconductor substrate;
selectively doping a low concentration P-type impurity into regions that become the source and the drain of the P-channel MOS transistor in the semiconductor substrate;
depositing a third insulating film on the semiconductor substrate;
etching the third insulating film by anisotropic dry etching to form side spacers on side walls of the first polycrystalline silicon film and the high melting point metal silicide film;
forming a second polycrystalline silicon film on the semiconductor substrate;
selectively doping a low concentration N-type impurity into the second polycrystalline silicon film to form a first N-type polycrystalline silicon region;
doping a low concentration P-type impurity into an entire region of the second polycrystalline silicon film to form a second P-type polycrystalline silicon region;
patterning the second polycrystalline silicon film to form a resistor;
selectively doping a high concentration N-type impurity into regions that become the source and the drain of the N-channel MOS transistor and a part or an entire region of the resistor formed of the first N-type region of the second polycrystalline silicon region; and
selectively doping a high concentration P-type impurity into regions that become the source and the drain of the P-channel MOS transistor and a part or an entire region of the resistor formed of the second P-type region of the second polycrystalline silicon.
Further, according to the present invention, there is provided a method of manufacturing a complementary MOS semiconductor device, comprising the steps of:
forming wells for defining respective regions of an N-channel MOS transistor and a P-channel MOS transistor in a semiconductor substrate;
forming an element isolating region on the semiconductor substrate;
forming a gate insulating film on the semiconductor substrate;
doping an impurity for controlling a threshold value into the semiconductor substrate;
forming a first polycrystalline silicon film on the semiconductor substrate;
selectively doping a low concentration N-type impurity into the first polycrystalline silicon film to form a first N-type polycrystalline silicon region;
selectively doping a high concentration P-type impurity into the first polycrystalline silicon film to form a first P-type polycrystalline silicon region in the first polycrystalline silicon film;
doping a low concentration P-type impurity into an entire region of the first polycrystalline silicon film to form a second P-type polycrystalline silicon region in the first polycrystalline silicon film;
patterning the first polycrystalline silicon film to form a gate electrode and a wiring formed of the first P-type region of the first polycrystalline silicon film and a resistor formed of the first N-type region and the second P-type region of the first polycrystalline silicon film;
doping a low concentration N-type impurity into the semiconductor substrate so that a source and a drain overlap a gate electrode of the N-channel MOS transistor in a planar manner
selectively doping a low concentration P-type impurity into the semiconductor substrate so that both a source and a drain or only the drain side thereof overlap a gate electrode of the P-channel MOS transistor in the planar manner;
selectively doping a high concentration N-type impurity into a part or an entire region of the resistor formed of the first N-type region of the first polycrystalline silicon film and the source and drain regions not overlapping the gate electrode of the N-channel MOS transistor in a planer manner; and
selectively doping a high concentration P-type impurity into a part or an entire region of the resistor formed of the second P-type region of the first polycrystalline silicon film and the region where both the source and the drain do not overlap the gate electrode of the P-channel MOS transistor in a planer manner or the region where the source side thereof overlaps the gate electrode in the planar manner an only the drain side thereof does not overlap the gate electrode in the planar manner.
Further, according to the present invention, there is provided a method of manufacturing a complementary MOS semiconductor device Further, according to the present invention, there is provided a, comprising the steps of:
forming wells or defining respective regions of an N-channel MOS transistor and a P-channel MOS transistor in a semiconductor substrate;
forming an element isolating region on the semiconductor substrate;
forming a gate insulating film on the semiconductor substrate;
doping an impurity for controlling a threshold value into the semiconductor substrate;
forming a first polycrystalline silicon film on the semiconductor substrate;
selectively doping a high concentration P-type impurity into the first polycrystalline silicon film to form a first P-type polycrystalline silicon region in the first polycrystalline silicon film;
patterning the first polycrystalline silicon film to form a gate electrode and a wiring formed of the first P-type region of the first polycrystalline silicon film and a resistor formed of the region other than the first P-type region of the first polycrystalline silicon film;
selectively doping a low concentration N-type impurity into the first polycrystalline silicon film other than the semiconductor substrate and the first P-type region where the source and the drain overlap the gate electrode of the N-channel MOS transistor in a planer manner to form first N-type regions in the low concentration N-type source and drain and the first polycrystalline silicon film;
selectively doping a low concentration P-type impurity into the first polycrystalline silicon film other than the semiconductor substrate, the first P-type region and the second N-type region where both the source and the drain or only the drain side thereof overlaps the gate electrode of the P-channel MOS transistor in a planer manner to form second P-type regions in the low concentration source and drain or only drain of the P-channel MOS transistor and the first polycrystalline silicon film;
selectively doping a high concentration N-type impurity into a part or an entire region of the resistor formed of the first N-type region or the first polycrystalline silicon film and the source and drain regions not overlapping the gate electrode of the N-channel MOS transistor in a planer manner; and
selectively doping a high concentration P-type impurity into a part or an entire region of the resistor formed of the second P-type region of the first polycrystalline silicon film and the region where both the source and the drain do not overlap the gate electrode of the P-channel MOS transistor in a planar manner or the region where the source side thereof overlaps the gate electrode in the planar manner and only the drain side thereof does not overlap the gate electrode in the planar manner.
Further, according to the present invention, there is provided a method of manufacturing a complementary MOS semiconductor device, comprising the steps of:
forming wells for defining respective regions of an N-channel MOS transistor and a P-channel MOS transistor in a semiconductor substrate;
forming an element isolating region on the semiconductor substrate;
forming a gate insulating film on the semiconductor substrate;
doping an impurity for controlling a threshold value into the semiconductor substrate;
forming a first polycrystalline silicon film on the semiconductor substrate;
doping a high concentration P-type impurity into the first polycrystalline silicon film to form a first P-type polycrystalline silicon region in the first polycrystalline silicon film;
patterning the first polycrystalline silicon film to form a gate electrode and a wiring formed of the first P-type region;
forming a fourth insulating film on the semiconductor substrate;
forming a second polycrystalline silicon film on the semiconductor substrate;
selectively doping a low concentration N-type impurity into the second polycrystalline silicon film to form a first N-type region in the second polycrystalline silicon film;
doping a low concentration P-type impurity into an entire region of the second polycrystalline silicon film to form a second P-type region in the second polycrystalline silicon film;
patterning the second polycrystalline silicon film to form a resistor;
doping a low concentration N-type impurity into the semiconductor substrate so that the source and the drain overlap the gate electrode of the N-channel MOS transistor in a planar manner;
doping a low concentration P-type impurity into the semiconductor substrate so that both the source and the drain or only the drain side thereof overlap the gate electrode of the P-channel MOS transistor in the planar manner;
selectively doping a high concentration N-type impurity into a part or an entire region of the resistor formed of he first N-type region of the second polycrystalline silicon film and the source and drain regions not overlapping the gate electrode of the N-channel MOS transistor in a planer manner; and
selectively doping a high concentration P-type impurity into a part or an entire region of the resistor formed of the second P-type region of the second polycrystalline silicon films and the region where both the source and the drain do not overlap the gate electrode of the P-channel MOS transistor in a planer manner or the region where the source side thereof overlaps the gate electrode in the planar manner and only the drain side thereof does not overlap the gate electrode in the planar manner.
Further, according to the present invention, there is provided a method of manufacturing a complementary MOS semiconductor device, comprising the steps of:
forming wells for defining respective regions of an N-channel MOS transistor and a P-channel MOS transistor in a semiconductor substrate;
forming an element isolating region on the semiconductor substrate;
forming a gate insulating film on the semiconductor substrate;
doping an impurity for controlling a threshold value into the semiconductor substrate;
forming a first polycrystalline silicon film on the semiconductor substrate;
doping a high concentration P-type impurity into the first polycrystalline silicon film to form a first P-type polycrystalline silicon region in the first polycrystalline silicon film;
patterning the first polycrystalline silicon film to form a gate electrode and a wiring formed of the first P-type region;
forming a fourth insulating film on the semiconductor substrate;
forming a second polycrystalline silicon film on the semiconductor substrate;
patterning the second polycrystalline silicon film to form a resistor;
selectively doping a low concentration N-type impurity into the region where source and the drain overlap the gate electrode of the N-channel MOS transistor in a planer manner and the second polycrystalline silicon film to simultaneously form first N-type regions in the low concentration source and drain of the N-channel MOS transistor and the second polycrystalline silicon film;
selectively doping a low concentration P-type impurity into the region where both the source and the drain or only the drain side thereof overlaps the gate electrode of the P-channel MOS transistor in a planer manner and the second polycrystalline silicon film to simultaneously form second P-type regions in the low concentration source and drain or drain of the P-channel MOS transistor and the second polycrystalline silicon film;
selectively doping a high concentration N-type impurity into a part or an entire region of the resistor formed of the first N-type region of the second polycrystalline silicon film and the source and drain regions not overlapping the gate electrode of the N-channel MOS transistor in a planer manner; and
selectively doping a high concentration P-type impurity into a part or an entire region of the resistor formed of the second P-type region of the second polycrystalline silicon film and the region where both the source and the drain do not overlap the gate electrode of the P-channel MOS transistor in a planer manner or the region where the source side thereof overlaps the gate electrode in a planar manner and only the drain side thereof does not overlap the gate electrode in the planar manner.
Further, according to the present invention, there is provided a method of manufacturing a complementary MOS semiconductor device, comprising the steps of:
forming wells for defining respective regions of an N-channel MOS transistor and a P-channel MOS transistor in a semiconductor substrate;
forming an element isolating region or the semiconductor substrate;
forming a gate insulating film on the semiconductor substrate;
doping an impurity for controlling a threshold value into the semiconductor substrate;
forming a first polycrystalline silicon film on the semiconductor substrate;
selectively doping a low concentration N-type impurity into the first polycrystalline silicon film to form a first N-type polycrystalline silicon region in the first polycrystalline silicon film;
selectively doping a high concentration P-type impurity into the first polycrystalline silicon film to form a first P-type polycrystalline silicon region in the first polycrystalline silicon film;
doping a low concentration P-type impurity into an entire region of the first polycrystalline silicon film to form a second P-type polycrystalline silicon region in the first polycrystalline silicon film;
forming a second insulating film on the first polycrystalline silicon film;
selectively removing the second insulating film on the first P-type region of the first polycrystalline silicon film;
forming a high melting point metal silicide film on the semiconductor substrate;
selectively removing the high melting point silicide film on the patterned second insulating film and in the vicinity thereof;
removing the patterned second insulating film;
patterning the first polycrystalline silicon film and the high melting point metal silicide film to form a gate electrode and a wiring formed of a lamination layer of the first P-type region of the first polycrystalline silicon film and the high melting point metal silicide film and a resistor region formed of the first N-type region of the first polycrystalline silicon film and the second P-type region;
doping a low concentration N-type impurity into the semiconductor substrate so that the source and the drain overlap the gate electrode of the N-channel type MOS transistor in the planar manner;
doping a low concentration P-type impurity into the semiconductor substrate so that both the source and the drain or only the drain side thereof overlaps the gate electrode of the P-type MOS transistor in the planar manner;
selectively doping a high concentration N-type impurity into a part or an entire region of the resistor formed of the first N-type region of the first polycrystalline silicon film and the source and drain regions not overlapping the gate electrode of the N-channel MOS transistor in the planer manner; and
selectively doping a high concentration P-type impurity into a part or an entire region of the resistor formed of the second P-type region of the first polycrystalline silicon film and the region where both the source and the drain do not overlap the gate electrode of the P-channel MOS transistor in a planer manner or the region where the source side thereof overlaps the gate electrode in a planar manner and only the drain side thereof does not overlap the gate electrode in the planar manner.
Further, according to the present invention, there is provided a method of manufacturing a complementary MOS semiconductor device, comprising the steps of:
forming wells for defining respective regions of an N-channel MOS transistor and a P-channel MOS transistor in a semiconductor substrate;
forming an element isolating region on the semiconductor substrate;
forming a gate insulating film on the semiconductor substrate;
doping an impurity for controlling a threshold value into the semiconductor substrate;
forming a first polycrystalline silicon film on the semiconductor substrate;
selectively doping a high concentration P-type impurity into the first polycrystalline silicon film to form a first P-type region in the first polycrystalline silicon film;
forming a second insulating film on the first polycrystalline silicon film;
selectively removing the second insulating film on the first P-type region of the first polycrystalline silicon film;
forming a high melting point metal silicide film on the semiconductor substrate;
selectively removing the high melting point silicide film on the patterned second insulating film and in the vicinity thereof;
removing the patterned second insulating film;
patterning the first polycrystalline silicon film and the high melting point metal silicide film to form a gate electrode and a wiring formed of a lamination layer of the first P-type region of the first polycrystalline silicon film and the high melting point metal silicide film and a resistor region formed of the region other than the first P-type region of the first polycrystalline silicon film;
selectively doping a low concentration N-type impurity into the region where the source and the drain overlap the gate electrode of the N-channel MOS transistor in a planer manner and the first polycrystalline silicon film, other than the first P-type region to simultaneously form first N-type regions in the low concentration source and drain of the N-channel MOS transistor and the first polycrystalline silicon film;
selectively doping a low concentration P-type impurity into the region where both the source and the drain or only the drain side thereof overlaps the gate electrode of the P-channel MOS transistor in a planer manner and the first polycrystalline silicon film other than the first P-type region and the first N-type region to simultaneously form second P-type regions in the low concentration source and drain or only drain of the P-channel MOS transistor and the first polycrystalline silicon film;
selectively doping a high concentration N-type impurity into a part or an entire region of the resistor formed of the first N-type region of the first polycrystalline silicon film and the source and drain regions not overlapping the gate electrode of the N-channel MOS transistor in the planer manner; and
selectively doping a high concentration P-type impurity into a part or an entire region of the resistor formed of the second P-type region of the first polycrystalline silicon film and the region where both the source and the drain do not overlap the gate electrode of the P-channel MOS transistor in a planer manner or the region where the source side thereof overlaps the gate electrode in a planar manner and only the drain side thereof does not overlap the gate electrode in the planar manner.
Further, according to the present invention, there is provided a method of manufacturing a complementary MOS semiconductor device, comprising the steps of:
forming wells for defining respective regions of an N-channel MOS transistor and a P-channel MOS transistor in a semiconductor substrate;
forming an element isolating region on the semiconductor substrate;
forming a gate insulating film on the semiconductor substrate;
doping an impurity for controlling a threshold value into the semiconductor substrate;
forming a first polycrystalline silicon film on the semiconductor substrate;
selectively doping a low concentration N-type impurity into the first polycrystalline silicon film to form a first N-type region in the first polycrystalline silicon film;
selectively doping a high concentration P-type impurity into the first polycrystalline silicon film to form a first P-type polycrystalline silicon region in the first polycrystalline silicon film;
doping a low concentration P-type impurity into an entire region of the first polycrystalline silicon film to form a second P-type polycrystalline silicon region in the first polycrystalline silicon film;
forming a second insulating film on the first polycrystalline silicon film;
selectively removing the second insulating film on the first P-type region of the first polycrystalline silicon film;
forming a high melting point metal film on the semiconductor substrate;
performing heat treatment for the high melting point metal film, which contacts to the first polycrystalline silicon film, to obtain a high melting point metal silicide film;
selectively removing non-reacted high melting point film on the second insulating film;
removing the patterned second insulating film;
patterning the first polycrystalline silicon film and the high melting point metal film to form a gate electrode and a wiring formed of a lamination layer of the first P-type region of the first polycrystalline silicon film and the high melting point metal silicide film and a resistor region formed of the first N-type region of the first polycrystalline silicon film and the second P-type region;
doping a low concentration N-type impurity into the semiconductor substrate so that the source and the drain overlap the gate electrode of the N-channel type MOS transistor in the planar manner;
doping a low concentration P-type impurity into the semiconductor substrate so that both the source and the drain or only the drain side thereof overlaps the gate electrode of the P-type MOS transistor in the planar manner;
selectively doping, a high concentration N-type impurity into a part or an entire region of the resistor formed of the first N-type region of the first polycrystalline silicon film and the source and drain regions not overlapping the gate electrode of the N-channel MOS transistor in the planer manner; and
selectively doping a high concentration P-type impurity into a part or an entire region of the resistor formed of the second P-type region of the first polycrystalline silicon film and the region where both the source and the drain do not overlap the gate electrode of the P-channel MOS transistor in a planer manner or the region where the source side thereof overlaps the gate electrode in a planar manner and only the drain side thereof does not overlap the gate electrode in the planar manner.
Further, according to the present invention, there is provided a method of manufacturing a complementary MOS semiconductor device, comprising the steps of:
forming wells for defining respective regions of an N-channel MOS transistor and a P-channel MOS transistor in a semiconductor substrate;
forming an element isolating region on the semiconductor substrate;
forming a gate insulating film on the semiconductor substrate;
doping an impurity for controlling a threshold value into the semiconductor substrate;
forming a first polycrystalline silicon film on the semiconductor substrate;
selectively doping a high concentration, P-type impurity into the first polycrystalline silicon film to form a first P-type region in the first polycrystalline silicon film;
forming a second insulating film on the first polycrystalline silicon film;
selectively removing the second insulating film on the first P-type region of the first polycrystalline silicon film;
forming a high melting point metal film or the semiconductor substrate;
performing heat treatment for the high melting point metal film, which contacts to the first polycrystalline silicon film, to obtain a high melting point metal silicide film;
selectively removing non-reacted high melting point film on the second insulating film;
removing the patterned second insulating film;
patterning the first polycrystalline silicon film and the high melting point metal silicide film to form a gate electrode and a wiring formed of a lamination layer of the first P-type region of the first polycrystalline silicon film and the high melting point metal silicide film and a resistor region formed of the region other than the first P-type region of the first polycrystalline silicon film;
selectively doping a low concentration N-type impurity into the region where the source and the drain overlap the gate electrode of the N-channel MOS transistor in a planer manner and the first polycrystalline silicon film other than the first P-type region to simultaneously form first N-type regions in the low concentration source and drain of the N-channel MOS transistor and the first polycrystalline silicon film;
selectively doping a low concentration P-type impurity into the region where both the source and the drain or only the drain side thereof overlaps the gate electrode of the P-channel MOS transistor in a planer manner and the first polycrystalline silicon film other than the first P-type region and the first N-type region to simultaneously form second P-type regions in the low concentration source and drain or only drain of the P-channel MOS transistor and the first polycrystalline silicon film;
selectively doping a high concentration N-type impurity into a part or an entire region of the resistor forced of the first N-type region of the first polycrystalline silicon film and the source and drain regions not overlapping the gate electrode of the N-channel MOS transistor in the planer manner; and
selectively doping a high concentration P-type impurity into a part or an entire region of the resistor formed of the second P-type region of the first polycrystalline silicon film and the region where both the source and the drain do not overlap the gate electrode of the P-channel MOS transistor in a planer manner or the region where the source side thereof overlaps the gate electrode in a planar manner and only the drain side thereof does not overlap the gate electrode in the planar manner.
Further, according to the present invention, there is provided a method of manufacturing a complementary MOS semiconductor device, comprising the steps of:
forming wells for defining respective regions of an N-channel MOS transistor and a P-channel MOS transistor in a semiconductor substrate;
forming an element isolating region on the semiconductor substrate;
forming a gate insulating film on the semiconductor substrate;
doping an impurity for controlling a threshold value into the semiconductor substrate;
forming a first polycrystalline silicon film on the semiconductor substrate;
doping a high concentration P-type impurity into the first polycrystalline silicon film to form a first P-type region in the first polycrystalline silicon film;
forming a high melting point metal silicide film on the first polycrystalline silicon film;
patterning the high melting point metal silicide film and the first polycrystalline silicon film to form a gate electrode and a wiring formed of a lamination layer of the first P-type region of the first polycrystalline silicon film and the high melting point metal silicide film;
forming a fourth insulating film on the semiconductor substrate;
forming a second polycrystalline silicon film on the semiconductor substrate;
selectively doping a low concentration N-type impurity into the second polycrystalline silicon film to form a first N-type region in the second polycrystalline silicon film;
doping a low concentration P-type impurity into an entire region of the second polycrystalline silicon film form a second P-type region in the second polycrystalline silicon film;
patterning the second polycrystalline silicon film to form a resistor;
doping a low concentration N-type impurity into the semiconductor substrate so that a source and a drain overlap a gate electrode of the N-channel MOS transistor in the planar manner;
selectively doping a low concentration P-type impurity into the semiconductor substrate so that both a source and a drain or only the drain side thereof overlaps a gate electrode of the P-channel MOS transistor in the planar manner;
selectively doping a high concentration N-type impurity into a part or an entire region of the resistor formed of the first N-type region of the second polycrystalline silicon film and the source and drain regions not overlapping the gate electrode of the N-channel MOS transistor in the planer manner; and
selectively doping a high concentration P-type impurity into a part or an entire region of the resistor formed of the second P-type region of the second polycrystalline silicon film and the region where both the source and the drain do not overlap the gate electrode of the P-channel MOS transistor in a planer manner or the region where the source side thereof overlaps the gate electrode in the planar manner and only the drain side thereof does not overlap the gate electrode in he planar manner.
Further, according to the present invention, there is provided a method of manufacturing a complementary MOS semiconductor device, comprising the steps of:
forming wells for defining respective regions of an N-channel MOS transistor and a P-channel MOS transistor in a semiconductor substrate;
forming an element isolating region on the semiconductor substrate;
forming a gate insulating film on the semiconductor substrate;
doping an impurity for controlling a threshold value into the semiconductor substrate;
forming a first polycrystalline silicon film on the semiconductor substrate;
doping a high concentration P-type impurity into the first polycrystalline silicon film to form a first P-type region in the first polycrystalline silicon film;
forming a high melting point metal silicide film on the first polycrystalline silicon film;
patterning the high melting point metal silicide film and the first polycrystalline silicon film to form a gate electrode and a wiring formed of a lamination layer of the first P-type region of the first polycrystalline silicon film and the high melting point metal silicide film;
forming a fourth insulating film on the semiconductor substrate;
forming a second polycrystalline silicon film on the semiconductor substrate;
patterning the second polycrystalline silicon film to form a resistor;
selectively doping a low concentration N-type impurity into the region where the source and the drain overlap the gate electrode of the N-channel MOS transistor in a planer manner and the second polycrystalline silicon film to simultaneously form first N-type regions in the low concentration source and drain of the N-channel MOS transistor and the second polycrystalline silicon film;
selectively doping a low concentration P-type impurity into the region where both the source and the drain or only the drain side thereof overlaps the gate electrode of the P-channel MOS transistor in a planer manner and the second polycrystalline silicon film to simultaneously form second P-type regions in the low concentration source and drain or the drain of the P-channel MOS transistor and the second polycrystalline silicon film;
selectively doping a high concentration N-type impurity into a part or an entire region of the resistor formed of the first N-type region of the second polycrystalline silicon film and the source and drain regions not overlapping the gate electrode of the N-channel MOS transistor in the planer manner; and
selectively doping a high concentration P-type impurity into a part or an entire region of the resistor formed of the second P-type region of the second polycrystalline silicon film and the region where both the source and the drain do not overlap the gate electrode of the P-channel MOS transistor in a planer manner or the region where the source side thereof overlaps the gate electrode in the planar manner and only the drain side thereof does not overlap the gate electrode in the planar manner.
Further, according to the present invention, there is provided a method of manufacturing a complementary MOS semiconductor device, comprising the steps of:
forming wells for defining respective regions of an N-channel MOS transistor and a P-channel MOS transistor in a semiconductor substrate;
forming an element isolating region on the semiconductor substrate;
forming a gate insulating film on the semiconductor substrate;
doping an impurity for controlling a threshold value into the semiconductor substrate;
forming a first polycrystalline silicon film on the semiconductor substrate;
doping a high concentration P-type impurity into the first polycrystalline silicon film to form a first P-type region in the first polycrystalline silicon film;
forming a high melting point metal film on the first polycrystalline silicon film;
performing heat treatment for the high melting point metal film, which contacts the first polycrystalline silicon film, to obtain a high melting point metal silicide film;
patterning the high melting point metal silicide film and the first polycrystalline silicon film to form a gate electrode and a wiring formed of a lamination layer of the first P-type region of the first polycrystalline silicon film and the high melting point metal silicide film;
forming a fourth insulating film on the semiconductor substrate;
forming a second polycrystalline silicon film on the semiconductor substrate;
selectively doping a low concentration N-type impurity into the second polycrystalline silicon film to form the first N-type region in the second polycrystalline silicon film;
doping a low concentration P-type impurity into an entire region of the second polycrystalline silicon film to form a second P-type region in the second polycrystalline silicon film;
patterning the second polycrystalline silicon film to form a resistor;
doping a low concentration N-type impurity into the semiconductor substrate so that the source and the drain overlap the gate electrode of the N-channel MOS transistor in a planar manner;
doping a low concentration P-type Impurity into the semiconductor substrate so that both the source and the drain or the drain overlaps the gate electrode of the P-channel MOS transistor in the planar manner;
selectively doping a high concentration N-type impurity into a part or an entire region of the resistor formed of the first N-type region of the second polycrystalline silicon film and the source and drain regions not overlapping the gate electrode of the N-channel MOS transistor in the plane manner; and
selectively doping a high concentration P-type impurity into a part or an entire region of the resistor formed of the second P-type region of the second polycrystalline silicon film and the region where both the source and the drain do not overlap the gate electrode of the P-channel MOS transistor in a planer manner or the region where the source side thereof overlaps the gate electrode In the planar manner and only the drain side thereof does not overlap the gate electrode in the planar manner.
Further, according to the present invention, there is provided a method of manufacturing a complementary MOS semiconductor device, comprising the steps of:
forming wells for defining respective regions of an N-channel MOS transistor and a P-channel MOS transistor in a semiconductor substrate;
forming an element isolating region on the semiconductor substrate;
forming a gate insulating film on the semiconductor substrate;
doping an impurity for controlling a threshold value into the semiconductor substrate;
forming a first polycrystalline silicon film on the semiconductor substrate;
doping a high concentration P-type impurity into the first polycrystalline silicon film to form a first P-type region in the first polycrystalline silicon film;
forming a high melting point metal film on the first polycrystalline silicon film;
performing heat treatment for the high melting point metal film, which contacts the first polycrystalline silicon film, to obtain a high melting point metal silicide film;
patterning the high melting point metal silicide film and the first polycrystalline silicon film to form a gate electrode and a wiring formed of a lamination layer of the first P-type region of the first polycrystalline silicon film and the high melting point metal silicide film;
forming a fourth insulating film on the semiconductor substrate;
forming a second polycrystalline silicon film on the semiconductor substrate;
patterning the second polycrystalline silicon film to form a resistor;
selectively doping a low concentration N-type Impurity into the region where source and the drain overlap the gate electrode of the N-channel MOS transistor in a planer manner and the second polycrystalline silicon film to simultaneously form first N-type regions in the low concentration source and drain of the N-channel MOS transistor and the second polycrystalline silicon film;
selectively doping a low concentration P-type impurity into the region where both the source and the drain or only the drain side thereof overlaps the gate electrode of the P-channel MOS transistor in a planer manner and the second polycrystalline silicon film to simultaneously form second P-type regions in the low concentration source and drain or drain of the P-channel MOS transistor and the second polycrystalline silicon film;
selectively doping a low concentration N-type impurity into a part or an entire region of the resistor formed of the first N-type region of the second polycrystalline silicon film and the source and drain regions not overlapping the gate electrode of the N-channel MOS transistor in the planer manner; and
selectively doping a high concentration P-type impurity into a part or an entire region of the resistor formed of the second P-type region of the second polycrystalline silicon film and the region where both the source and the drain do not overlap the gate electrode of the P-channel MOS transistor in a planer manner or the region where the source side thereof overlaps the gate electrode in the planar manner and only the drain side thereof does not overlap the gate electrode in the planar manner.
Further, according to the present invention, there is provided a method of manufacturing a complementary MOS semiconductor device, comprising the steps of:
forming wells for defining respective regions of an N-channel MOS transistor and a P-channel MOS transistor in a semiconductor substrate;
forming an element isolating region on the semiconductor substrate;
forming a gate insulating film on the semiconductor substrate;
doping an impurity for controlling a threshold value into the semiconductor substrate;
forming a first polycrystalline silicon film on the semiconductor substrate;
doping a high concentration P-type impurity into an entire region of the first polycrystalline silicon film to form a first P-type region in the first polycrystalline silicon film;
forming a high melting point metal silicide film on the first polycrystalline silicon film;
forming a first insulating film on the high melting point metal silicide film;
patterning the first insulating film, the high melting point metal silicide film and the first polycrystalline silicon film to form a gate electrode and a wiring;
forming a fourth insulating film on the semiconductor substrate;
forming a second polycrystalline silicon film on the semiconductor substrate;
selectively doping a low concentration N-type impurity into the second polycrystalline silicon film to form a first N-type region in the second polycrystalline silicon film;
doping a low concentration P-type impurity into an entire region of the second polycrystalline silicon film to on a second P-type region in the second polycrystalline silicon film;
patterning the second polycrystalline silicon film to form a resistor;
selectively doping a low concentration N-type impurity into the semiconductor substrate so that both a source and a drain or only the drain side thereof overlaps the gate electrode of the N-channel MOS transistor in a planar manner;
selectively doping a low concentration P-type impurity into the semiconductor substrate so that both the source and the drain or only the drain side thereof overlaps the gate electrode of the P-channel MOS transistor in the planar manner;
selectively doping a low concentration N-type impurity into a part or an entire region of the resistor formed of the first N-type region of the second polycrystalline silicon film and the source and drain regions not overlapping the gate electrode of the N-channel MOS transistor in the planer manner, or the region where the source side thereof overlaps the gate electrode in a planar manner and only the drain side thereof does not overlap the gate electrode in the planar manner; and
selectively doping a high concentration P-type impurity into a part or an entire region of the resistor formed of the second P-type region of the second polycrystalline silicon film and the region where both the source and the drain do not overlap the gate electrode of the P-channel MOS transistor in a planer manner or the region where the source side thereof overlaps the gate electrode in the planar manner and only the drain side thereof does not overlap the gate electrode in the planar manner.
Further, according to the present invention, there is provided a complementary MOS semiconductor device, characterized in that the semiconductor substrate is a P-type semiconductor substrate, and regions of the N-channel MOS transistor and the P-channel MOS transistor are defined by forming an N-type well, respectively.
Further, according to the present invention, there is provided a complementary MOS semiconductor device, characterized in that the semiconductor substrate is a P-type semiconductor substrate, and regions of the N-channel MOS transistor and the P-channel MOS transistor are defined by forming an N-type well and a P-type well, respectively.
Further, according to the present invention, there is provided a complementary MOS semiconductor device, characterized in that the semiconductor substrate is an N-type semiconductor substrate, and regions of the N-channel MOS transistor and the P-channel MOS transistor are defined by forming a P-type well, respectively.
Further, according to the present invention, there is provided a complementary MOS semiconductor device, characterized in that the semiconductor substrate is an N-type semiconductor substrate, and regions of the N-channel MOS transistor and the P-channel MOS transistor are defined by forming an N-type well and a P-type well, respectively.
Further, according to the present invention, there is provided a method of manufacturing a complementary MOS semiconductor device, characterized in that the semiconductor substrate is a P-type semiconductor substrate, and regions of the N-channel MOS transistor and the P-channel MOS transistor are defined by forming an N-type well, respectively.
Further, according to the present invention, there is provided a method of manufacturing a complementary MOS semiconductor device, characterized in that the semiconductor substrate is a P-type semiconductor substrate, and regions of the N-channel MOS transistor and the P-channel MOS transistor are defined by forming an N-type well and a P-type well, respectively.
Further, according to the present invention, there is provided a method of manufacturing a complementary MOS semiconductor device, characterized in that the semiconductor substrate is an N-type semiconductor substrate, and regions of the N-channel MOS transistor and the P-channel MOS transistor are defined by forming a P-type well, respectively.
Further, according to the present invention, there is provided method of manufacturing a complementary MOS semiconductor device, characterized in that the semiconductor substrate is an N-type semiconductor substrate, and regions of the N-channel MOS transistor and the P-channel MOS transistor are defined by forming an N-type well and a P-type well, respectively.
Further, according to the present invention, there is provided a method of manufacturing a complementary MOS semiconductor device, characterized in that the step of forming the element isolating region on the semiconductor substrate is performed by a LOCOS method.
Further, according to the present invention, there is provided a method of manufacturing a complementary MOS semiconductor device, characterized in that the step of forming the element isolating region on the semiconductor substrate is performed by a shallow trench isolation method.
Further, according to the present invention, there is provided a method of manufacturing a complementary MOS semiconductor device, characterized in that the step of doping the impurity for the threshold control is performed by an ion injection method, and the impurity for the threshold control of the N-channel MOS transistor is arsenic or phosphorous.
Further, according to the present invention, there is provided a complementary MOS semiconductor device, characterized in that the first polycrystalline silicon is formed by a chemical vapor deposition method.
Further, according to the present invention, there is provided a complementary MOS semiconductor device, characterized in that the second polycrystalline silicon is formed by a chemical vapor deposition method or a sputtering method.
Further, according to the present invention, there is provided a method of manufacturing a complementary MOS semiconductor device, characterized in that the first polycrystalline silicon is formed by a chemical vapor deposition method.
Further, according to the present invention, there is provided a method of manufacturing a complementary MOS semiconductor device, characterized in that the second polycrystalline silicon is formed by a chemical vapor deposition method or a sputtering method,
Further, according to the present invention, there is provided a method of manufacturing a complementary MOS semiconductor device, characterized in that the first P-type region of the first polycrystalline silicon is formed by an ion injection method using boron or BF2 as an impurity, a pre-deposition and drive-in method in an electric furnace using boron as an impurity or a molecular layer doping method using boron as the impurity.
Further, according to the present invention, there is provided a method of manufacturing a complementary MOS semiconductor device, characterized in that the step of forming the first P-type region of the first polycrystalline silicon is performed by a chemical vapor deposition method for depositing polycrystalline silicon and simultaneously doping boron as an impurity.
Further, according to the present invention, there is provided a method of manufacturing a complementary MOS semiconductor device, characterized in that the first insulating film is a silicon oxide film formed by a chemical vapor deposition method or a thermal oxidization method and has a film thickness in a range of 1000 xc3x85 to 2000 xc3x85.
Further, according to the present invention, there is provided a method of manufacturing a complementary MOS semiconductor device, characterized in that the first insulating film is a silicon oxide film formed by a chemical vapor deposition method and has a film thickness in a range of 1000 xc3x85 to 2000 xc3x85.
Further, according to the present invention, there is provided a method of manufacturing a complementary MOS semiconductor device, characterized in that a lower layer of the first insulating film is a silicon oxide film formed by a chemical vapor deposition method or a thermal oxidization method; an upper layer thereof is formed by the chemical vapor deposition method; and a total film thickness of the first insulating is in a range of 1000 xc3x85 to 3000 xc3x85.
Further, according to the present invention, there is provided a method of manufacturing a complementary MOS semiconductor device, characterized in that the second insulating film is formed by a chemical vapor deposition method and has a film thickness in a range of 1000 xc3x85 to 4000 xc3x85.
Further, according to the present invention, there is provided a method of manufacturing a complementary MOS semiconductor device, characterized in that the method insulating film is a silicon oxide film formed by a chemical vapor deposition method and has a total film thickness in a range of 2000 xc3x85 to 6000 xc3x85.
Further, according to the present invention, there is provided a complementary MOS semiconductor device, characterized in that the high melting point metal silicide is formed by a chemical vapor deposition method or a sputtering method.
Further, according to the present invention, there is provided a method of manufacturing a complementary MOS semiconductor device, characterized in that the high melting point metal silicide is formed by a chemical vapor deposition method or a sputtering method.
Further, according to the present invention, there is provided a method of manufacturing a complementary MOS semiconductor device, characterized in that the high melting point metal is cobalt or titanium formed by a sputtering method and has a film thickness in a range of 100 xc3x85 to 500 xc3x85.
Further, according to the present invention, there is provided a semiconductor device, characterized in that, in a reference voltage circuit in which a gate and a drain of an enhancement NMOS transistor in which the gate and the drain are short-circuited, are connected to a gate and a source of a depletion NMOS transistor in which the gate and the source are short-circuited, and the connection node is used as an output node, the polarities of gate electrodes of the enhancement NMOS transistor and the depletion NMOS transistor are a P-type.
Further, according to the present invention, there is provided a semiconductor device, characterized in that, in a reference voltage circuit in which a source of an enhancement NMOS transistor in which the gate and the drain are short-circuited, is connected to a drain of a depletion NMOS transistor in which the gate and the source are short-circuited, and the connection node is used as an output node, the polarities of gate electrodes of the enhancement NMOS transistor and the depletion NMOS transistor are a P-type.
Further, according to the present invention, there is provided a semiconductor device, characterized in that, in a reference voltage circuit in which a gate and a drain of an enhancement NMOS transistor in which the gate and the drain are short-circuited, are connected to a source of a depletion NMOS transistor in which a gate is short-circuited with a source of the enhancement NMOS transistor and the connection node is used as an output node, the polarities of gate electrodes of the enhancement NMOS transistor and she depletion NMOS transistor are a P-type.
Further, according to the present invention, there is provided a semiconductor device, characterized in that, in a reference voltage circuit in which: a drain of a depletion NMOS transistor in which a gate and a source are short-circuited is connected to a drain and a gate of a first enhancement PMOS transistor in which a source is connected to a power supply; a drain of a second enhancement PMOS transistor in which a source is connected to a power supply and a gate is connected commonly to the first enhancement PMOS transistor is connected to a gate and a drain of an enhancement NMOS transistor in which the gate and the drain are short-circuited; and the connection node is used as an output node, the polarities of gate electrodes of the enhancement NMOS transistor and the depletion NMOS transistor are a P-type.
Further, according to the present invention, there is provided a semiconductor device, characterized in that, in a reference voltage circuit in which: a drain of a first depletion NMOS transistor in which a gate and a source are short-circuited, is connected to a gate and a source of a second depletion NMOS transistor in which the gate and the source are short-circuited; a drain of the second depletion NMOS transistor is connected to a power supply; the source of the first depletion NMOS transistor is connected to an enhancement NMOS transistor in which a gate and a drain are short-circuited; and the connection node is used as an output node, the polarities of gate electrodes of the enhancement NMOS transistor, the first depletion NMOS transistor, and the second depletion NMOS transistor are a P-type.
Further, according to the present invention, there is provided a semiconductor device, characterized in that, in a reference voltage circuit in which: a gate and a drain of an enhancement NMOS transistor in which the gate and the drain are short-circuited, are connected with a source of a first depletion NMOS transistor in which a gate is connected to a source of the enhancement NMOS transistor; a drain of the first depletion NMOS transistor is connected to a gate and a source of a second depletion NMOS transistor in which the gate and the source are short-circuited; a drain of the second depletion NMOS transistor is connected to a power supply; and the connection node of the drain of the enhancement NMOS transistor and the source of the first depletion NMOS transistor is used as an output node, the polarities of gate electrodes of the enhancement NMOS transistor, the first depletion NMOS transistor, and the second depletion NMOS transistor are a P-type.